US 12,484,274 B2
Techniques for semiconductor gate and contact formation to reduce seam formation
Hsin-Han Tsai, Hsinchu (TW); Hsiang-Ju Liao, Hsinchu (TW); Yi-Lun Li, Hsinchu (TW); Cheng-Lung Hung, Hsinchu (TW); Weng Chang, Hsin-Chu (TW); Chi On Chui, Hsinchu (TW); Jo-Chun Hung, Hsinchu (TW); Chih-Wei Lee, New Taipei (TW); and Chia-Wei Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 22, 2022, as Appl. No. 17/660,241.
Prior Publication US 2023/0343834 A1, Oct. 26, 2023
Int. Cl. H10D 64/01 (2025.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/66 (2025.01)
CPC H10D 64/01 (2025.01) [H01L 21/76883 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 64/666 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a plurality of nanostructure channels over a semiconductor substrate and arranged along a direction perpendicular to the semiconductor substrate;
a fin structure adjacent to the plurality of nanostructure channels; and
a gate structure wrapping around each of the plurality of nanostructure channels,
wherein the gate structure comprises ruthenium, and
wherein the ruthenium comprises a plurality of grains that have a median size in a range from approximately six nanometers (nm) to approximately fifteen nm.