| CPC H10D 62/8171 (2025.01) [H10D 30/0297 (2025.01); H10D 30/668 (2025.01); H10D 62/153 (2025.01); H10D 62/154 (2025.01); H10D 84/83 (2025.01)] | 17 Claims |
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1. A power semiconductor device comprising:
a semiconductor layer of silicon carbide (SiC);
a plurality of well regions disposed in the semiconductor layer such that two adjacent well regions at least partially make contact with each other, and having a second conductive type, wherein, as viewed from a plan view, the plurality of well regions includes seven well regions adjacent to each other and a center of each of the seven well regions is disposed at either a center of a regular hexagon or a vertex of the regular hexagon;
a plurality of source regions disposed on the plurality of well regions, respectively, in the semiconductor layer, and having a first conductive type opposite to the second conductive type;
a drift region disposed in the semiconductor layer while extending to a surface of the semiconductor layer from lower portions of the plurality of well regions through a region between the plurality of well regions, and having the first conductive type;
a plurality of trenches disposed to be recessed into the semiconductor layer from the surface of the semiconductor layer, wherein each trench connects two source regions of the plurality of source regions to each other while passing through a contact portion between the adjacent well regions of the plurality of well regions;
a gate insulating layer disposed on an inner wall of each of the plurality of trenches;
a gate electrode layer disposed on the gate insulating layer and including a first part disposed in each of the plurality of trenches and a second part disposed on the semiconductor layer; and
a pillar region positioned under each of the plurality of well regions to make contact with the drift region and the plurality of well regions in the semiconductor layer, and having the second conductive type.
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