| CPC H10D 62/137 (2025.01) [H01L 21/268 (2013.01); H10D 12/01 (2025.01); H10D 62/133 (2025.01); H10D 62/8325 (2025.01)] | 11 Claims |
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1. A semiconductor device comprising:
a semiconductor substrate;
a collector region of a first conductive type that is formed on a lower surface of the semiconductor substrate;
a first semiconductor region of a second conductive type that differs from the first conductive type, the first semiconductor region being formed on the collector region in the semiconductor substrate;
a second semiconductor region of the first conductive type, the second semiconductor region being formed from an upper surface of the semiconductor substrate to an intermediate depth in the first semiconductor region;
an emitter region of the second conductive type, the emitter region being formed from an upper surface of the second semiconductor region to an intermediate depth of the second semiconductor region, the emitter region being spaced apart from the first semiconductor region;
a gate electrode formed on the semiconductor substrate by way of an insulation film in a state where the gate electrode covers the second semiconductor region between the emitter region and the first semiconductor region;
a silicide layer being formed in a state where the silicide layer is brought into contact with a lower surface of the collector region; and
a collector electrode being formed in a state where the collector electrode is brought into contact with a lower surface of the silicide layer, wherein
the collector region, the emitter region and the gate electrode form an insulation bipolar transistor,
the silicide layer contains aluminum, a first bonding metal which is bonded with silicon, and a second bonding metal which is bonded with carbon, and
the semiconductor substrate contains silicon carbide.
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