US 12,484,265 B2
Subtractive source drain contact for stacked devices
Heng Wu, Santa Clara, CA (US); Junli Wang, Slingerlands, NY (US); Ruilong Xie, Niskayuna, NY (US); Albert M. Young, Fishkill, NY (US); Albert M. Chu, Nashua, NH (US); Brent A. Anderson, Jericho, VT (US); and Ravikumar Ramachandran, Pleasantville, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 22, 2022, as Appl. No. 17/808,124.
Prior Publication US 2023/0420502 A1, Dec. 28, 2023
Int. Cl. H10D 62/10 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 62/121 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a field effect transistor (“FET”) stack, the FET stack comprising a lower FET on a substrate, an upper FET vertically aligned and stacked on top of the lower FET and a dielectric layer between the lower FET and the upper FET; and
a first contact to a lower source drain of the lower FET, wherein the first contact comprises a tapered profile such that a width of a lower surface of the first contact is wider than a width of an upper surface of the first contact.