US 12,484,258 B2
Flash memory cell structure having separate program and erase electron paths
Thomas S. Chung, Kissimmee, FL (US); Maxim Klebanov, Palm Coast, FL (US); Sundar Chetlur, Frisco, TX (US); and James McClay, Dudley, MA (US)
Assigned to Allegro MicroSystems, LLC, Manchester, NH (US)
Filed by Allegro MicroSystems, LLC, Manchester, NH (US)
Filed on Feb. 9, 2022, as Appl. No. 17/650,418.
Prior Publication US 2023/0253507 A1, Aug. 10, 2023
Int. Cl. G11C 16/14 (2006.01); G11C 16/10 (2006.01); H10D 30/01 (2025.01); H10D 30/68 (2025.01); H10D 62/13 (2025.01)
CPC H10D 30/683 (2025.01) [G11C 16/10 (2013.01); G11C 16/14 (2013.01); H10D 30/0411 (2025.01); H10D 62/151 (2025.01)] 29 Claims
OG exemplary drawing
 
1. A flash memory cell comprising:
a well having a first-type dopant;
a source having a second-type dopant and formed within the well;
a drain having the second-type dopant and formed within the well;
a floating gate above the well, wherein the floating gate has a first edge overlapping with the source and a second edge overlapping with the drain;
a control gate above the floating gate;
an oxide compound disposed between the floating gate and the control gate;
a tunnel oxide disposed between the floating gate and the well,
wherein the flash memory cell is configured, in one of a program mode or an erase mode, to move an electron from the source to the floating gate,
wherein the flash memory cell is configured, in the other one of the program or the erase mode, to move an electron from the floating gate to the drain, and
wherein the control gate extends around at least three sides of the floating gate, and wherein the oxide compound extends around at least three sides of the floating gate; and
a first layer disposed on an opposite side of the well as the floating gate, the first layer having a second-type dopant to form a first p-n junction with the well to provide a diode.