| CPC H10D 30/6755 (2025.01) [H10D 30/6734 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/471 (2025.01); H10D 86/60 (2025.01)] | 5 Claims |
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1. A semiconductor device comprising:
a first transistor comprising:
a first gate electrode;
an oxide semiconductor layer overlapping the first gate electrode;
a source electrode and a drain electrode each overlapping the oxide semiconductor layer; and
a second gate electrode overlapping a central portion of the oxide semiconductor layer;
a second transistor connected to the first gate electrode and the second gate electrode; and
a metal wiring line provided between the second gate electrode and the second transistor, wherein
the oxide semiconductor layer is provided between the first gate electrode and the second gate electrode in a cross-sectional view,
the oxide semiconductor layer includes a first channel formation region overlapping the second gate electrode and a second channel formation region not overlapping the second gate electrode in a plan view,
a resistance value between the second gate electrode and the second transistor is higher than a resistance value between the first gate electrode and the second transistor, and
the metal wiring has a higher resistance value than that of a wiring line provided between the first gate electrode and the second transistor.
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