| CPC H10D 30/6737 (2025.01) [H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6743 (2025.01); H10D 84/013 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01)] | 20 Claims |
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1. An integrated circuit (IC) structure comprising:
a first transistor comprising first source/drain regions and a first gate structure between the first source/drain regions;
first gate spacers spacing apart the first source/drain regions from the first gate structure from a plan view;
a second transistor comprising second source/drain regions and a second gate structure between the second source/drain regions;
second gate spacers spacing apart the second source/drain regions from the second gate structure from the plan view, the first gate spacers and the second gate spacers extending along a first direction from the plan view;
a backside metal line extending between the first transistor and the second transistor along a second direction from the plan view;
a first metal contact wrapping around a first one of the second source/drain regions and having a protrusion interfacing the backside metal line from a cross-sectional view; and
a silicide layer interfacing an entirety of a sidewall of the first one of the second source/drain regions.
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