| CPC H10D 30/6735 (2025.01) [H01L 21/02499 (2013.01); H10D 30/6757 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |

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1. A method, comprising:
providing an opening above a semiconductor substrate;
depositing a catalyst layer along a surface of the opening;
performing a selectivity enhancement process, wherein the selectivity enhancement process alters a deposition rate of a metal component on at least one region of the catalyst layer; and
depositing the metal component on the catalyst layer.
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