US 12,484,251 B2
Multigate device structure with engineered gate
Hsiao-Chun Chang, Hsinchu County (TW); and Guan-Jie Shen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 4, 2022, as Appl. No. 17/832,595.
Claims priority of provisional application 63/255,478, filed on Oct. 14, 2021.
Prior Publication US 2023/0118779 A1, Apr. 20, 2023
Int. Cl. H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 30/024 (2025.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0147 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a fin region formed on a substrate, wherein the fin region includes multiple channels vertically stacked on the substrate;
a gate stack disposed on the fin region, wherein the gate stack is wrapping around each of the multiple channels, and wherein the gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer;
a pair of source/drain (S/D) features formed on the fin region, interposed by the gate stack, and connected with the multiple channels; and
inner spacers disposed on sidewalls of the pair of S/D features, wherein the gate stack includes gate extensions that overlapped with the inner spacers.