| CPC H10B 63/80 (2023.02) [H10B 63/10 (2023.02); H10B 63/24 (2023.02)] | 18 Claims |
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1. A variable resistance memory device, comprising:
a substrate;
a cell array region on the substrate, the cell array region including:
memory cells, each of the memory cells including a switching pattern and a variable resistance pattern,
first conductive lines extending in a first direction,
second conductive lines extending in a second direction intersecting the first direction, the memory cells being at intersections of the first conductive lines and the second conductive lines, and
through vias extending through the cell array region without contacting the first conductive lines and without contacting the second conductive lines;
a peripheral circuit region on the substrate between the cell array region and the substrate, the peripheral circuit region including a lower wiring structure;
a wiring region on the cell array region with the cell array region between the wiring region and the peripheral circuit region, the wiring region including an inter-wiring insulating film and an upper wiring structure in the inter-wiring insulating film; and
a protective film between the cell array region and the wiring region, the protective film covering an upper surface of the cell array region,
wherein the first conductive lines and the second conductive lines are electrically connected to the lower wiring structure, the through vias are electrically connected to the lower wiring structure, and the upper wiring structure is electrically connected to the through vias.
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