US 12,484,231 B2
Ferroelectric memory structure
Jyun-Hong Shih, Hsinchu (TW); and Min-Cheng Chen, Hsinchu County (TW)
Assigned to Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed by Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed on Jul. 20, 2023, as Appl. No. 18/356,176.
Claims priority of application No. 112114619 (TW), filed on Apr. 19, 2023.
Prior Publication US 2024/0357827 A1, Oct. 24, 2024
Int. Cl. H10B 51/20 (2023.01); H01L 23/528 (2006.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 23/5283 (2013.01); H10B 51/10 (2023.02); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A ferroelectric memory structure, comprising:
a substrate;
a first conductive line located on the substrate;
a first dielectric layer located on the first conductive line;
a channel pillar located on the first conductive line and located in the first dielectric layer;
a second conductive line located on the first dielectric layer and the channel pillar;
a gate pillar passing through the second conductive line and located in the channel pillar;
a second dielectric layer located between the gate pillar and the first conductive line, between the gate pillar and the channel pillar, and between the gate pillar and the second conductive line; and
a ferroelectric material layer located between the gate pillar and the second dielectric layer.