US 12,484,226 B2
Three-dimensional NAND memory device and method that eliminate leakage currents and short circuits
Longxiang Yan, Wuhan (CN); Wei Xu, Wuhan (CN); Bo Xu, Wuhan (CN); Fazhan Wang, Wuhan (CN); Lei Xue, Wuhan (CN); and Zongliang Huo, Wuhan (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed on Jul. 11, 2022, as Appl. No. 17/862,191.
Prior Publication US 2024/0015973 A1, Jan. 11, 2024
Int. Cl. H01L 21/425 (2006.01); H10B 43/35 (2023.01); H10B 99/00 (2023.01)
CPC H10B 43/35 (2023.02) [H01L 21/425 (2013.01); H10B 99/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of forming a three-dimensional (3D) NAND memory device, comprising:
forming a gate line slit through a plurality of alternating layers of an oxide layer and a conductive material layer, wherein the gate line slit extends along a first direction perpendicular to the alternating layers of the oxide layer and the conductive material layer and also extends along a second direction perpendicular to the first direction and is formed to separate memory cells into blocks, and the conductive material layer is further formed on a sidewall and a bottom of the gate line slit;
performing an ion implantation process to dope at least a portion of the conductive material layer that is on the bottom and a portion of the sidewall of the gate line slit; and
performing an etch process in the gate line slit to remove the conductive material layer that is weakened by the ion implantation process to at least remove a portion of the conductive material layer from between adjacent oxide layers, providing a recessed surface of the conductive material layer between the adjacent oxide layers and exposed to the gate line slit.