| CPC H10B 43/20 (2023.02) [G11C 8/14 (2013.01); G11C 16/08 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a first stack of alternating first word line layers and first insulating layers over a semiconductor layer, the first stack including a first array region and a first staircase region adjacent to the first array region;
a first channel structure extending from the semiconductor layer and through the first array region of the first stack;
a second stack of alternating second word line layers and second insulating layers over the first stack, the second stack including a second array region over the first array region and a second staircase region adjacent to the second array region and over the first staircase region; and
a second channel structure extending from the first channel structure and through the second array region of the second stack,
wherein in the first array region, a thickness of a particular first insulating layer, which is positioned closest to the second stack relative to other first insulating layers, is a sum of at least two times an average thickness of the other first insulating layers and at least one time an average thickness of the first word line layers in the first array region,
wherein in the first staircase region, the first stack includes a multi-layer structure including sequentially:
a first layer of the first insulating layers,
a first layer of the first word line layers,
a second layer of the first insulating layers,
a second layer of the first word line layers, and
a third layer of the first insulating layers,
wherein the multi-layer structure in the first staircase region is co-planar with the particular first insulating layer in the first array region.
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