US 12,484,217 B2
Embedded flash memory device with floating gate embedded in a substrate
Wei Cheng Wu, Zhubei (TW); and Harry-Hak-Lay Chuang, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 4, 2024, as Appl. No. 18/404,676.
Application 17/231,204 is a division of application No. 16/231,066, filed on Dec. 21, 2018, abandoned.
Application 14/980,147 is a division of application No. 13/924,331, filed on Jun. 21, 2013, granted, now 9,230,977, issued on Jan. 5, 2016.
Application 18/404,676 is a continuation of application No. 17/231,204, filed on Apr. 15, 2021, granted, now 11,903,191.
Application 16/231,066 is a continuation of application No. 14/980,147, filed on Dec. 28, 2015, granted, now 10,163,919, issued on Dec. 25, 2018.
Prior Publication US 2024/0147716 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 41/30 (2023.01); H01L 21/306 (2006.01); H01L 21/321 (2006.01); H10B 10/00 (2023.01); H10B 41/49 (2023.01); H10B 43/00 (2023.01); H10B 43/30 (2023.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10B 41/30 (2023.02) [H01L 21/30604 (2013.01); H01L 21/3212 (2013.01); H10B 41/49 (2023.02); H10B 43/00 (2023.02); H10B 43/30 (2023.02); H10D 64/017 (2025.01); H10D 64/035 (2025.01); H10D 84/0144 (2025.01); H10D 84/038 (2025.01); H10B 10/18 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
etching a semiconductor substrate to form a recess extending into a first region of the semiconductor substrate; and
forming a first transistor in the first region and a second transistor in a second region of the semiconductor substrate, forming the first transistor and the second transistor comprising:
forming a bottom dielectric layer in the first region and the second region, a portion of the bottom dielectric layer being in the recess;
forming a charge storage layer over the bottom dielectric layer in the first region and the second region, a portion of the charge storage layer being in the recess;
removing the charge storage layer from the second region, the portion of the charge storage layer being level with an upper surface of the bottom dielectric layer;
forming a top dielectric layer directly over the charge storage layer and the bottom dielectric layer in the first region and the second region;
removing the top dielectric layer and the bottom dielectric layer from the second region to expose the semiconductor substrate;
forming an oxide layer over the second region of the semiconductor substrate;
forming a high-k dielectric layer over the top dielectric layer and the oxide layer;
forming a gate layer over the high-k dielectric layer;
patterning from the gate layer to the semiconductor substrate to form a first stack in the first region and a second stack in the second region; and
forming a first gate spacer along a first sidewall of the first stack and a second gate spacer along a second sidewall of the second stack, the first gate spacer being in physical contact with the bottom dielectric layer and the top dielectric layer.