| CPC H10B 12/20 (2023.02) [G11C 11/34 (2013.01); G11C 11/39 (2013.01); G11C 11/40 (2013.01); H10B 80/00 (2023.02); H10B 99/20 (2023.02)] | 19 Claims |
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1. A memory structure, comprising:
a substrate having an upper surface;
a first gate structure, a second gate structure and a third gate structure disposed on the substrate, separated from each other along a first direction and extending along a second direction and a third direction, respectively; and
a plurality of channel bodies separated from each other and passing through the first gate structure, the second gate structure and the third gate structure along the first direction,
wherein the first direction, the second direction and the third direction are intersected with each other, the upper surface is parallel to the first direction and the second direction, and a normal direction of the upper surface is parallel to the third direction;
wherein the second gate structure is disposed between the first gate structure and the third gate structure, the first gate structure comprises a first island structure, a second island structure and a third island structure, the third gate structure comprises a fourth island structure, a fifth island structure and a sixth island structure, the first island structure, the second island structure and the third island structure respectively extend along the third direction and are separated from each other along the second direction; the fourth island structure, the fifth island structure and the sixth island structure respectively extend along the third direction and are separated from each other along the second direction, wherein a height of the first island structure, the second island structure or the third island structure in the third direction is equal to a height of the second gate structure in the third direction, and a width of the first island structure, the second island structure or the third island structure in the second direction is smaller than a width of the second gate structure in the second direction.
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