US 12,484,207 B2
SRAM with channel count contrast for greater read stability
Clifford Ong, Portland, OR (US); Leonard Guler, Hillsboro, OR (US); Mohammad Hasan, Aloha, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/560,913.
Prior Publication US 2023/0209798 A1, Jun. 29, 2023
Int. Cl. H01L 27/11 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 10/00 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01)
CPC H10B 10/125 (2023.02) [H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A static random-access memory (SRAM) bit-cell structure, comprising:
a pass-gate transistor structure of n-type conductivity, comprising a first gate electrode around a stack of a first number of active channel regions comprising a crystalline material, and an inactive channel region also comprising the crystalline material;
a pull-down transistor structure of n-type conductivity, the pull-down transistor structure comprising a second gate electrode around a stack of a second number of active channel regions, greater than the first number of channel regions; and
a pull-up transistor, wherein the pull-up transistor further comprises a third gate electrode around a stack of a third number of active channel regions, and wherein the third number of active channel regions is different than the first number of active channel regions.