US 12,484,197 B2
Systems and methods for a top side cooled power semiconductor thermal interface spacer
Alexandre M. S. Reis, Westfield, IN (US); Bryan Alan Rohl, Westfield, IN (US); and Thomas Alan Degenkolb, Noblesville, IN (US)
Assigned to BorgWarner US Technologies LLC, Wilmington, DE (US)
Filed by BorgWarner US Technologies LLC, Wilmington, DE (US)
Filed on Mar. 13, 2023, as Appl. No. 18/182,482.
Prior Publication US 2024/0314979 A1, Sep. 19, 2024
Int. Cl. H05K 7/20 (2006.01); H01L 23/367 (2006.01); H01L 23/40 (2006.01); H01L 25/11 (2006.01)
CPC H05K 7/20445 (2013.01) [H01L 23/3675 (2013.01); H05K 7/209 (2013.01); H01L 23/40 (2013.01); H01L 25/115 (2013.01); H01L 2225/06589 (2013.01); H01L 2225/1094 (2013.01); H05K 7/20436 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A power semiconductor package comprising:
a first power semiconductor;
a cold plate including a floor and a first pedestal extending from the floor, wherein the first pedestal is configured to support the first power semiconductor;
a thermal interface material configured to transfer heat from the first power semiconductor to the first pedestal of the cold plate; and
a spacer including:
a first frame configured to receive at least a portion of the first pedestal, and
a second frame configured to receive the thermal interface material;
wherein the spacer is configured to provide a uniform thickness of the thermal interface material between the first pedestal of the cold plate and the first power semiconductor.