US 12,484,156 B2
Electroplating edge connector pins of printed circuit boards without using tie bars
Mingyi Yu, Saratoga, CA (US); and Gregory Patrick Bodi, Santa Cruz, CA (US)
Assigned to NVIDIA CORPORATION, Santa Clara, CA (US)
Filed by NVIDIA CORPORATION, Santa Clara, CA (US)
Filed on May 8, 2023, as Appl. No. 18/314,054.
Application 18/314,054 is a division of application No. 17/186,868, filed on Feb. 26, 2021, granted, now 11,653,455.
Prior Publication US 2023/0276578 A1, Aug. 31, 2023
Int. Cl. H05K 3/00 (2006.01); H05K 1/11 (2006.01); H05K 3/04 (2006.01); H05K 3/24 (2006.01)
CPC H05K 3/242 (2013.01) [H05K 1/117 (2013.01); H05K 3/0047 (2013.01); H05K 3/043 (2013.01); H05K 2201/0347 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A printed circuit board, comprising:
a laminate substrate that includes at least one electrically insulating layer;
a plurality of edge connector pins that are formed on the at least one electrically insulating layer and includes:
a first edge connector pin that is configured as a ground connector pin and is coupled to a tie bar stub, wherein the tie bar stub includes a gold electroplated layer and was connected to a removable portion of a plating conductor; and
a second edge connector pin that is configured as a signal connector pin and is not coupled to a tie bar stub; and
a hole that includes a portion of an edge of the first edge connector pin and a portion of an edge of the second edge connector pin, wherein the first edge connector pin is adjacent to the second edge connector pin.