US 12,483,732 B2
Encoder, decoder, encoding method, and decoding method
Virginie Drugeon, Darmstadt (DE); Tadamasa Toma, Osaka (JP); Takahiro Nishi, Nara (JP); Kiyofumi Abe, Osaka (JP); and Yusuke Kato, Osaka (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA, Torrance, CA (US)
Filed by Panasonic Intellectual Property Corporation of America, Torrance, CA (US)
Filed on Jul. 25, 2024, as Appl. No. 18/783,785.
Application 18/783,785 is a continuation of application No. 17/535,873, filed on Nov. 26, 2021, granted, now 12,143,639.
Application 17/535,873 is a continuation of application No. PCT/JP2020/023906, filed on Jun. 18, 2020.
Claims priority of provisional application 62/862,952, filed on Jun. 18, 2019.
Prior Publication US 2024/0380925 A1, Nov. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 19/70 (2014.01); H04N 19/463 (2014.01)
CPC H04N 19/70 (2014.11) [H04N 19/463 (2014.11)] 4 Claims
OG exemplary drawing
 
1. An encoder comprising:
memory; and
circuitry coupled to the memory,
wherein in operation, the circuitry:
stores first information indicating a number of temporal sub-layers into a buffering period supplemental enhancement information (SEI) message; and
generates a bitstream including the buffering period SEI message and a picture timing SEI message, wherein
the picture timing SEI message includes a loop structure repeated the number of times indicated by the first information, and each of loops includes a parameter related to a timing to extract data from a coded picture buffer (CPB).