US 12,483,446 B2
Receiver circuit, corresponding isolated driver device, electronic system and method of decoding a differential signal into a digital output signal
Valerio Gennari Santori, Milan (IT); Carlo Curina, Bareggio (IT); Valerio Bendotti, Vilminore di Scalve (IT); and Nicola De Campo, Cura Carpignano (IT)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Dec. 6, 2023, as Appl. No. 18/531,568.
Claims priority of application No. 102022000026067 (IT), filed on Dec. 20, 2022.
Prior Publication US 2024/0205055 A1, Jun. 20, 2024
Int. Cl. H04L 25/02 (2006.01); H03K 5/24 (2006.01)
CPC H04L 25/0292 (2013.01) [H03K 5/2481 (2013.01); H04L 25/0266 (2013.01); H04L 25/0272 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A receiver circuit, comprising:
a pair of input nodes configured to receive a differential signal therebetween, the differential signal including spikes of a first polarity and spikes of a second polarity;
a first receiver circuit comparator circuit configured to receive the differential signal and output an intermediate set signal that includes a pulse at each spike of the differential signal having the first polarity;
a second receiver circuit comparator circuit configured to receive the differential signal and output an intermediate reset signal that includes a pulse at each spike of the differential signal having the second polarity;
a sensing circuit coupled to the pair of input nodes and configured to extract a common-mode voltage signal from the differential signal and to assert at least one control signal in response to an amplitude of the common-mode voltage signal exceeding a threshold value;
a logic circuit configured to:
receive the intermediate set signal, the intermediate reset signal and the at least one control signal;
assert a masking signal for a masking time interval in response to the at least one control signal being asserted, and de-assert the masking signal in response to the masking time interval elapsing;
produce a corrected set signal by passing the intermediate set signal when the masking signal is de-asserted and masking the intermediate set signal when the masking signal is de-asserted, wherein the corrected set signal includes the pulses of the intermediate set signal produced while the masking signal is de-asserted; and
produce a corrected reset signal by passing the intermediate reset signal when the masking signal is de-asserted and masking the intermediate reset signal when the masking signal is de-asserted, wherein the corrected reset signal includes the pulses of the intermediate reset signal produced while the masking signal is de-asserted; and
an output control circuit configured to:
receive the corrected set signal and the corrected reset signal; and
assert a digital output signal in response to a pulse being detected in the corrected set signal and de-assert the digital output signal in response to a pulse being detected in the corrected reset signal.