| CPC H04L 7/0012 (2013.01) [H03L 7/06 (2013.01)] | 20 Claims |

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1. A transceiver circuitry comprising:
clock generation circuitry configured to generate a first clock signal; and
first receiver circuitry configured to:
receive the first clock signal and a first input signal;
generate a first frequency offset value based on the first input signal and the first clock signal, wherein the first input signal has a first frequency and the first clock signal has a second frequency different than the first frequency; and
output the first frequency offset value.
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