US 12,483,353 B2
Decoder success predictor signaling for adjusting MIRS scheduling policy
Amit Bar-Or Tillinger, Tel-Aviv (IL); Gideon Shlomo Kutz, Ramat Hasharon (IL); Assaf Touboul, Netanya (IL); and Tal Oved, Modiin (IL)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 14, 2024, as Appl. No. 18/442,001.
Application 18/442,001 is a division of application No. 17/822,560, filed on Aug. 26, 2022, granted, now 11,923,977.
Prior Publication US 2024/0187133 A1, Jun. 6, 2024
Int. Cl. H04L 1/00 (2006.01); H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC H04L 1/005 (2013.01) [H03M 13/1105 (2013.01); H03M 13/611 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for wireless communication at a network node comprising:
memory; and
at least one processor coupled to the memory and, based at least in part on information stored in the memory, the at least one processor is configured to:
obtain an indication of whether a user equipment (UE) is capable of skipping decoding of code blocks;
select at least one of an incremental value from a plurality of incremental values or a modulation and coding scheme (MCS) from a plurality of MCSs for a multiple incremental redundancy scheme (MIRS) of a transmission and a set of retransmissions of the transmission in response to the indication indicating that the UE is capable of skipping decoding of code blocks; and
output the transmission for the UE based on the selection of at least one of the incremental value or the MCS for the MIRS of the transmission and the set of retransmissions of the transmission.