| CPC H04J 3/0667 (2013.01) [H04J 3/0641 (2013.01); H04J 3/0664 (2013.01); H04J 3/0682 (2013.01); H04L 7/0033 (2013.01)] | 18 Claims |

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10. A computing device for synchronizing time across a plurality of time domains between a master node and a slave node, the computing device comprising:
one or more processors;
a communication interface configured to communicate with external devices;
a memory configured to load a computer program that is executed by the processor; and
a storage configured to store the computer program,
wherein the computer program includes computer-executable instructions for causing, when executed in the computing device, the computing device to perform method operations comprising:
transmitting, by a precision time protocol (PTP) layer of the master node, a reference time indicated by a hardware clock of the master node to a PTP layer of the slave node;
synchronizing, by the PTP layer of the slave node, a hardware clock of the slave node to the reference time indicated by the hardware clock of the master node;
transmitting, by an offset clock layer of the master node, an offset of a first time domain among the plurality of time domains to an offset clock layer of the slave node;
obtaining, by the PTP layer of the slave node, the time in the first time domain by applying the offset of the first time domain to a reference time indicated by the hardware clock of the slave node;
transmitting, by the offset clock layer of the master node, an offset of a second time domain among the plurality of time domains to the offset clock layer of the slave node; and
obtaining, by the PTP layer of the slave node, a time in the second time domain by applying the offset (θ2) of the second time domain to the reference time indicated by the hardware clock of the slave node.
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