US 12,483,276 B2
Error detection
Thomas Kern, Aschheim (DE); Alexander Klockmann, Taufkirchen (DE); and Michael Goessel, Mahlow (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Jan. 29, 2024, as Appl. No. 18/424,922.
Claims priority of application No. 10 2023 102 337.3 (DE), filed on Jan. 31, 2023.
Prior Publication US 2024/0257893 A1, Aug. 1, 2024
Int. Cl. H03M 13/37 (2006.01); G11C 29/42 (2006.01); H03M 13/00 (2006.01); H03M 13/51 (2006.01)
CPC H03M 13/3738 (2013.01) [G11C 29/42 (2013.01); H03M 13/51 (2013.01); H03M 13/6505 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for error detection, comprising:
reading a first byte sequence from memory;
correcting the first byte sequence based on an error code to generate a second byte sequence;
determining that a byte of the second byte sequence is impermissible when the byte is not equal to an assigned byte of the first byte sequence and if no error of a predefined error set corrupts the byte to the assigned byte of the first byte sequence; and
in response to determining that at least one byte of the second byte sequence is impermissible, providing indication of a false error correction.