US 12,483,263 B2
Comparison circuit, analog-to-digital converter circuit, and semiconductor integrated circuit
Hidetaka Haneda, Kanagawa (JP)
Assigned to SOCIONEXT INC., Yokohama (JP)
Filed by Socionext Inc., Kanagawa (JP)
Filed on Sep. 25, 2023, as Appl. No. 18/473,823.
Claims priority of application No. 2022-161652 (JP), filed on Oct. 6, 2022.
Prior Publication US 2024/0120936 A1, Apr. 11, 2024
Int. Cl. H03M 1/46 (2006.01)
CPC H03M 1/462 (2013.01) [H03M 1/466 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A comparison circuit, comprising:
a differential comparison circuit configured to perform comparison determination of differential input signals based on an internal clock signal and generate first differential output signals indicating a result of the comparison determination;
a determination assist circuit configured to receive the first differential output signals output from the differential comparison circuit and generate second differential output signals provided to a latch circuit, the determination assist circuit being configured to vary at least one value of the first differential output signals from a reset value and generate the second differential output signals when a designed time has elapsed with values of the first differential output signals being unvaried from the reset value since the start of an operation of the comparison determination in the differential comparison circuit;
the latch circuit configured to latch the second differential output signals and generate third differential output signals; and
a clock generation circuit configured to generate the internal clock signal based on the third differential output signals.