US 12,483,257 B2
Dynamic current mismatch accumulation schemes for digital-to-analog converters
Sarthak Kalani, Santa Clara, CA (US); Andrew Weil, San Diego, CA (US); and John Abcarius, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Dec. 27, 2023, as Appl. No. 18/397,835.
Prior Publication US 2025/0219647 A1, Jul. 3, 2025
Int. Cl. H03M 1/10 (2006.01); H03M 1/06 (2006.01); H03M 1/08 (2006.01); H03M 1/74 (2006.01)
CPC H03M 1/1033 (2013.01) [H03M 1/0653 (2013.01); H03M 1/0863 (2013.01); H03M 1/1095 (2013.01); H03M 1/742 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A digital-to-analog converter (DAC) circuit comprising:
a plurality of DAC cells, each DAC cell comprising a current source, a first switch coupled between the current source and a DAC output node, and a second switch coupled between the current source and a complementary DAC output node;
a reference cell comprising a reference current source, a third switch coupled between the reference current source and the complementary DAC output node, and a fourth switch coupled between the reference current source and the DAC output node;
a capacitive element;
an integrator comprising a first input coupled to a first terminal of the capacitive element and a second input coupled to a second terminal of the capacitive element;
a first set of switches configured to selectively couple the first terminal of the capacitive element to the DAC output node and the second terminal of the capacitive element to the complementary DAC output node; and
a second set of switches configured to selectively couple the second terminal of the capacitive element to the DAC output node and the first terminal of the capacitive element to the complementary DAC output node.