US 12,483,256 B2
Successive approximation register analog-to-digital converter with programmable sampling noise cancellation
Michael Todd Berens, Austin, TX (US); Khoi Mai, Austin, TX (US); Ashutosh Jain, Pensacola, FL (US); and Dylan John Rosser, Austin, TX (US)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Aug. 31, 2023, as Appl. No. 18/459,219.
Prior Publication US 2025/0080127 A1, Mar. 6, 2025
Int. Cl. H03M 1/12 (2006.01); H03M 1/08 (2006.01)
CPC H03M 1/08 (2013.01) 20 Claims
OG exemplary drawing
 
1. An analog-to-digital converter (ADC) comprising:
a digital-to-analog converter (DAC);
a comparator coupled to an output of the DAC, the comparator comprising a preamplifier and a latch, wherein an input of the preamplifier is coupled to the output of the DAC and an input of the latch is coupled to an output of the preamplifier;
a successive approximation register (SAR) logic unit coupled to an output of the latch and configured to generate a control signal for the comparator; and
a programmable delay unit configured to delay the control signal, such that the comparator receives the control signal and a delayed control signal, wherein the programmable delay unit is configured to adjust a delay between the control signal and the delayed control signal based on at least one parameter; and
wherein the programmable delay unit is configured to implement a first delay between the control signal and the delayed control signal for a first input signal provided to the DAC and a second delay between the control signal and the delayed control signal for a second input signal.