US 12,483,228 B2
Latch circuit and method of operating the same
Tsung-Ching (Jim) Huang, Mountain View, CA (US); Chan-Hong Chern, Palo Alto, CA (US); Ming-Chieh Huang, San Jose, CA (US); Chih-Chang Lin, San Jose, CA (US); and Tien-Chun Yang, San Jose, CA (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on May 25, 2023, as Appl. No. 18/323,583.
Application 15/960,847 is a division of application No. 14/630,941, filed on Feb. 25, 2015, granted, now 9,966,935, issued on May 8, 2018.
Application 18/323,583 is a continuation of application No. 15/960,847, filed on Apr. 24, 2018, granted, now 11,677,388.
Prior Publication US 2023/0299756 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 3/356 (2006.01); G11C 7/06 (2006.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 3/3562 (2006.01)
CPC H03K 3/356104 (2013.01) [G11C 7/065 (2013.01); H03K 3/012 (2013.01); H03K 3/037 (2013.01); H03K 3/3562 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A latch circuit, comprising:
a first power supply node configured to carry a first supply voltage during each of a first state of a clock signal and a second state of the clock signal;
a second power supply node configured to carry a second supply voltage during each of the first state of the clock signal and the second state of the clock signal, the second supply voltage having a value below a value of the first supply voltage;
a first input node;
a second input node;
a first output node;
a second output node;
a first switching device coupled between the first output node and the second output node, the first switching device being configured to be turned on in response to the first state of the clock signal and to be turned off in response to the second state of the clock signal;
a first transistor coupled between the second output node and the second power supply node;
a second transistor coupled between the first output node and the second power supply node;
a second switching device coupled between a gate of the first transistor and the first input node, the second switching device being configured to be turned on in response to the first state of the clock signal and to be turned off in response to the second state of the clock signal; and
a third switching device coupled between a gate of the second transistor and the second input node, the third switching device being configured to be turned on in response to the first state of the clock signal and to be turned off in response to the second state of the clock signal,
wherein, during the first state of the clock signal, one of the first transistor or the second transistor is configured to be part of a low resistance path from the first power supply node to the second power supply node.