US 12,483,220 B2
High resolution attenuator or phase shifter with weighted bits
Vikas Sharma, Reading (GB); and Peter Bacon, Derry, NH (US)
Assigned to MURATA MANUFACTURING CO., LTD., Nagaokakyo (JP)
Filed by Murata Manufacturing Co., Ltd., Nagaokakyo (JP)
Filed on Jul. 11, 2024, as Appl. No. 18/770,370.
Application 18/770,370 is a continuation of application No. 18/082,360, filed on Dec. 15, 2022, granted, now 12,040,769.
Application 18/082,360 is a continuation of application No. 17/115,368, filed on Dec. 8, 2020, granted, now 11,533,037, issued on Dec. 20, 2022.
Application 17/115,368 is a continuation of application No. PCT/US2019/037810, filed on Jun. 18, 2019.
Application PCT/US2019/037810 is a continuation of application No. 16/013,844, filed on Jun. 20, 2018, granted, now 10,505,511, issued on Dec. 10, 2019.
Prior Publication US 2025/0015775 A1, Jan. 9, 2025
Int. Cl. H03H 11/20 (2006.01); H03H 7/20 (2006.01); H03H 7/25 (2006.01); H03H 11/24 (2006.01); H03K 17/687 (2006.01)
CPC H03H 7/25 (2013.01) [H03H 7/20 (2013.01); H03H 11/20 (2013.01); H03H 11/245 (2013.01); H03K 17/687 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic circuit, including:
(a) multiple stages, each stage configured to selectively alter the attenuation or phase of an applied signal, each stage having an input port and an output port, each stage being assigned one of N bit positions where N is greater than or equal to 1, each stage being digitally selectable by an associated control line to be either in a reference state in which a received input signal applied at the input port is conducted to the output port, or in an active signal alteration state;
(b) wherein each stage is configured to provide a value of signal alteration;
(c) wherein the value of signal alteration for each stage assigned a bit position has a weight set by application of a weighting function; and
(d) wherein the multiple stages enable selection of 2N combinations of stages to provide a total range of signal alteration, the total range of signal alteration having a smallest level of signal alteration and a largest level of signal alteration, and to provide multiple levels of signal alteration within the total range of signal alteration between the smallest and the largest levels of signal alteration, wherein each of the multiple levels of signal alteration has a resolution less than the value of signal alteration of any one stage of the multiple stages.