US 12,483,027 B2
Transistor stack circuit
Ching-Yao Pai, Taipei (TW); and Yu-Hung Chen, Taipei (TW)
Assigned to RichWave Technology Corp., Taipei (TW)
Filed by RichWave Technology Corp., Taipei (TW)
Filed on Dec. 27, 2023, as Appl. No. 18/397,960.
Claims priority of application No. 112144251 (TW), filed on Nov. 16, 2023.
Prior Publication US 2025/0167542 A1, May 22, 2025
Int. Cl. H02H 9/04 (2006.01)
CPC H02H 9/046 (2013.01) [H02H 9/044 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A transistor stack circuit, comprising:
a first signal transmission port;
a second signal transmission port;
a plurality of transistors, connected in series to each other, and coupled between the first signal transmission port and the second signal transmission port;
a plurality of first resistors, wherein each of the first resistors has a first terminal and a second terminal, the first terminals are coupled to a common path, and each of the second terminals is coupled to a control terminal of a corresponding transistor among the transistors; and
an impedance unit, coupled between the common path and a reference voltage terminal, wherein
when an electrostatic discharge event occurs, an impedance value of the impedance unit is greater than twice of a resistance value of each of the first resistors, and the transistors form a low-impedance path.