| CPC H01P 1/36 (2013.01) [H03M 5/16 (2013.01)] | 18 Claims |

|
1. A digital isolator, comprising:
a) an encoding circuit configured to receive an input digital signal, and to encode a rising edge and a falling edge of the input digital signal into different coded signals;
b) an isolating element coupled to the encoding circuit, and being configured to transmit the coded signals in an electrical isolation manner; and
c) a decoding circuit configured to receive the coded signal through the isolation element, and to decode the coded signal to obtain the rising edge and the falling edge, in order to output an output digital signal consistent with the input digital signal,
d) wherein the rising edge of the input digital signal is encoded as a first pulse sequence, and the falling edge of the input digital signal is encoded as a second pulse sequence different from the first pulse sequence, and
e) wherein the encoding circuit is configured to output each of the coded signals after detecting the rising edge and the falling edge, and the encoding circuit is configured to output the rising edge after detecting the first pulse sequence and to output the falling edge after detecting the second pulse sequence.
|