US 12,482,779 B2
Hybrid backside thermal structures for enhanced ic packages
Feras Eid, Chandler, AZ (US); Joe Walczyk, Tigard, OR (US); Weihua Tang, Chandler, AZ (US); Akhilesh Rallabandi, Chandler, AZ (US); and Marco Aurelio Cartas Ayala, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 1, 2024, as Appl. No. 18/593,775.
Application 18/593,775 is a continuation of application No. 16/785,014, filed on Feb. 7, 2020, granted, now 11,948,906.
Prior Publication US 2024/0203926 A1, Jun. 20, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/29 (2013.01) [H01L 2224/29287 (2013.01); H01L 2224/29293 (2013.01); H01L 2224/29324 (2013.01); H01L 2224/29339 (2013.01); H01L 2224/29347 (2013.01); H01L 2924/14 (2013.01); H01L 2924/351 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an integrated circuit (IC) die comprising integrated circuitry over a first side of a material layer comprising silicon, and a second side of the IC die opposite the first side of the material layer; and
a composite layer on the second side of the IC die, wherein the composite layer comprises:
a first constituent material having a first linear coefficient of thermal expansion (CTE) and a first thermal conductivity, the first thermal conductivity exceeding that of the material layer; and
a second constituent material having a second CTE, the second CTE lower than the first CTE by at least 5 ppm/K, and a second thermal conductivity exceeding that of the material layer, wherein the composite layer comprises particles of one of the first or second constituent materials embedded within another of the first or second constituent materials.