US 12,482,775 B2
Semiconductor structure
Sheng-Fu Huang, New Taipei (TW); and Shing-Yih Shih, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Aug. 8, 2022, as Appl. No. 17/818,003.
Prior Publication US 2024/0047395 A1, Feb. 8, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/08 (2013.01) [H01L 24/05 (2013.01); H01L 25/0657 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/0236 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/024 (2013.01); H01L 2224/05687 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08146 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/3511 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first chip comprising:
a first semiconductor substrate;
a first multi-level interconnect structure over the first semiconductor substrate, the first multi-level interconnect structure comprising a conductive line;
a first redistribution layer (RDL) over the conductive line of the first multi-level interconnect structure;
a compact layer over the first RDL and the first multi-level interconnect structure, wherein the compact layer has a portion within the first multi-level interconnect structure;
a cap layer over the compact layer; and
a metal pad on the first RDL; and
a second chip bonded to the first chip, the second chip comprising:
a second semiconductor substrate;
a second multi-level interconnect structure over the second semiconductor substrate; and
a conductive structure extending from the second multi-level interconnect structure to the metal pad.