US 12,482,769 B2
Selective plating for packaged semiconductor devices
Katleen Fajardo Timbol, Allen, TX (US); and Jeffrey Salvacion Solas, Angeles (PH)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Jun. 30, 2022, as Appl. No. 17/855,695.
Prior Publication US 2024/0006351 A1, Jan. 4, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01)
CPC H01L 24/03 (2013.01) [H01L 24/02 (2013.01); H01L 24/04 (2013.01); H01L 24/05 (2013.01); H01L 24/32 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 21/561 (2013.01); H01L 2224/02215 (2013.01); H01L 2224/03001 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/03831 (2013.01); H01L 2224/0391 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05026 (2013.01); H01L 2224/05027 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05084 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05562 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05664 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/45565 (2013.01); H01L 2224/45664 (2013.01); H01L 2224/48105 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92247 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/04953 (2013.01); H01L 2924/07025 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A packaged semiconductor device, comprising:
a semiconductor die having a device side surface and an opposing backside surface, the backside surface mounted to a die pad of a lead frame using a die attach, the lead frame comprising conductive leads spaced from the die pad;
a conductor layer overlying the device side surface;
bond pads including bond pad conductors formed on the conductor layer, a nickel layer over the bond pad conductors, and a palladium or gold layer over the nickel layer;
conductor traces formed on the conductor layer, the conductor traces free from the nickel layer and the palladium or gold layer;
bond wires bonded to the palladium or gold layer of the bond pads, and electrically coupling the bond pads to conductive leads of the lead frame; and
mold compound covering the semiconductor die, the bond pads, the bond wires, and portions of the lead frame, wherein portions of the conductive leads are exposed from the mold compound to form terminals of the packaged semiconductor device.