US 12,482,764 B2
Semiconductor package including power plane connecting power terminal of passive device unit and dummy bump of interposer
Juyoun Choi, Hwaseong-si (KR); Miyeon Kim, Hwaseong-si (KR); and Jungil Son, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 28, 2022, as Appl. No. 17/875,639.
Claims priority of application No. 10-2021-0158036 (KR), filed on Nov. 16, 2021.
Prior Publication US 2023/0154866 A1, May 18, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 23/562 (2013.01) [H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/14 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/14517 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/1205 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a package base substrate including a potential plate;
an interposer arranged on the package base substrate and comprising at least one interposer through electrode, at least one first connection bump, and at least one second connection bump;
a first stacked chip unit arranged on the interposer and comprising a first semiconductor chip and at least one second semiconductor chip arranged on the first semiconductor chip; and
at least one passive device unit arranged on the package base substrate, the at least one passive device unit is spaced apart from the interposer in a horizontal direction parallel to an upper surface of the package base substrate,
wherein the at least one first connection bump is a dummy bump, and
the potential plate connects the at least one first connection bump and a power terminal of the at least one passive device unit to each other.