US 12,482,760 B2
Semiconductor structure and manufacturing method thereof
Dong Xue, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and CHANGXIN JIDIAN (BEIJING) MEMORY TECHNOLOGY CO., LTD., Beijing (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and CHANGXIN JIDIAN (BEIJING) MEMORY TECHNOLOGIES CO., LTD., Beijing (CN)
Filed on Jun. 10, 2022, as Appl. No. 17/806,361.
Claims priority of application No. 202210462528.5 (CN), filed on Apr. 29, 2022.
Prior Publication US 2023/0352420 A1, Nov. 2, 2023
Int. Cl. H01L 23/544 (2006.01)
CPC H01L 23/544 (2013.01) [H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
an interconnecting line layer, wherein the interconnecting line layer comprises a first region and a second region, and the first region of the interconnecting line layer comprises a first alignment mark;
an isolation structure, wherein the isolation structure is disposed in the second region of the interconnecting line layer; and
a redistribution layer, wherein the redistribution layer conformally covers the first region of the interconnecting line layer and the isolation structure, the redistribution layer comprises a second alignment mark, and the second alignment mark is located above the first alignment mark;
the first alignment mark comprises a plurality of first sub-marks, and the second alignment mark comprises a plurality of second sub-marks; and
a spacing between adjacent first sub-marks is a first spacing, a spacing between adjacent second sub-marks is a second spacing, and the second spacing is 80% to 98% of the first spacing.