US 12,482,759 B2
Wafer-level ASIC 3D integrated substrate, packaging device and preparation method
Yenheng Chen, Jiangyin (CN); Chengchung Lin, Jiangyin (CN); Jangshen Lin, Jiangyin (CN); and Mingchih Chen, Jiangyin (CN)
Assigned to SJ Semiconductor(Jiangyin) Corporation, Jiangyin (CN)
Filed by SJ Semiconductor(Jiangyin) Corporation, Jiangyin (CN)
Filed on Jun. 28, 2022, as Appl. No. 17/851,752.
Claims priority of application No. 202110721425.1 (CN), filed on Jun. 28, 2021; and application No. 202121466583.9 (CN), filed on Jun. 28, 2021.
Prior Publication US 2022/0415816 A1, Dec. 29, 2022
Int. Cl. H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5389 (2013.01) [H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 2224/12105 (2013.01); H01L 2924/15311 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A method for preparing a plurality of water-level ASIC 3D integrated substrates, comprising:
providing a carrier;
forming a separation layer on the carrier;
forming a first wiring layer on the separation layer, wherein the first wiring layer comprises a first dielectric layer and a first metal wire layer, wherein the first metal wire layer is exposed from a top surface of the first dielectric layer;
forming a conductive pillar on the first wiring layer, wherein the conductive pillar is electrically connected to the first metal wire layer;
forming a molding layer, wherein the molding layer molds the conductive pillar, and wherein the conductive pillar is exposed from a top surface of the molding layer;
forming a second wiring layer on the molding layer, wherein the second wiring layer comprises a second dielectric layer and a second metal wire layer, wherein the second metal wire layer is exposed from a top surface of the second dielectric layer, and wherein the second metal wire layer is electrically connected to the conductive pillar;
forming solder balls on the second wiring layer, wherein the solder balls are electrically connected to the second metal wire layer; and
peeling off the carrier at the separation layer to expose a surface of the first wiring layer away from the conductive pillar.