US 12,482,757 B2
Semiconductor packages and methods of manufacturing thereof
Ming-Fa Chen, Hsinchu (TW); Yun-Han Lee, Hsinchu (TW); and Lee-Chung Lu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 29, 2022, as Appl. No. 17/897,648.
Prior Publication US 2024/0071941 A1, Feb. 29, 2024
Int. Cl. H01L 23/52 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01)
CPC H01L 23/5386 (2013.01) [H01L 21/486 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0655 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H01L 23/5385 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/13081 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features;
a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and
an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures;
wherein:
the interposer includes a plurality of power rails configured to deliver power to the first and second chips;
the first chip further includes a plurality of third interconnect structures disposed opposite the first device features from the first interconnect structures; and
the second chip further includes a plurality of fourth interconnect structures disposed opposite the second device features from the second interconnect structures.