US 12,482,756 B2
Connectivity layer in 3D devices
Zachary Blair, San Jose, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Aug. 2, 2022, as Appl. No. 17/879,670.
Prior Publication US 2024/0047364 A1, Feb. 8, 2024
Int. Cl. H01L 23/538 (2006.01); G06F 12/1027 (2016.01); G06F 15/78 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5386 (2013.01) [G06F 12/1027 (2013.01); G06F 15/7825 (2013.01); H01L 23/5382 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06541 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A stack, comprising:
a first semiconductor die comprising a plurality of regularly arranged processing blocks;
a second semiconductor die comprising a plurality of irregularly arranged I/O blocks, wherein at least two of the plurality of I/O blocks are configured to connect to different types of external components, and wherein the external components are disposed on a same side of an interposer as the stack; and
a connectivity die disposed between the first die and the second die in the stack, the connectivity die comprising configurable interconnects configured to permit the plurality of processing blocks to communicate with the plurality of I/O blocks.