US 12,482,744 B2
Subtractively patterned interconnect structures for integrated circuits
Kevin Lin, Beaverton, OR (US); Noriyuki Sato, Hillsboro, OR (US); Tristan Tronic, Aloha, OR (US); Michael Christenson, Beaverton, OR (US); Christopher Jezewski, Portland, OR (US); Jiun-Ruey Chen, Hillsboro, OR (US); James M. Blackwell, Portland, OR (US); Matthew Metz, Portland, OR (US); Miriam Reshotko, Portland, OR (US); Nafees Kabir, Hillsboro, OR (US); Jeffery Bielefeld, Forest Grove, OR (US); Manish Chandhok, Beaverton, OR (US); Hui Jae Yoo, Hillsboro, OR (US); Elijah Karpov, Portland, OR (US); Carl Naylor, Portland, OR (US); and Ramanan Chebiam, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 17, 2024, as Appl. No. 18/668,038.
Application 18/668,038 is a continuation of application No. 17/841,551, filed on Jun. 15, 2022, granted, now 12,027,458.
Application 17/841,551 is a continuation of application No. 17/087,519, filed on Nov. 2, 2020, granted, now 11,444,024, issued on Sep. 13, 2022.
Prior Publication US 2024/0304543 A1, Sep. 12, 2024
Int. Cl. H01L 23/522 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/32139 (2013.01); H01L 21/76819 (2013.01); H01L 21/7682 (2013.01); H01L 21/76843 (2013.01); H01L 23/5283 (2013.01); H01L 23/53209 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure comprising:
a plurality of transistors; and
an interconnect structure coupled to the transistors, wherein the interconnect structure comprises:
a via and a dielectric material adjacent to the via;
a line in direct physical contact with the via, wherein the line extends over the dielectric material, and wherein a top width of the line is smaller than a bottom width of the line, wherein the via has a first chemical composition and the line has a second composition, different than the first chemical composition; and
a bottom barrier material between the line and the dielectric material.