US 12,482,743 B2
Interconnect structure and method for forming the same
Hsin-Yen Huang, New Taipei (TW); Shao-Kuan Lee, Kaohsiung (TW); Cheng-Chin Lee, Taipei (TW); Hai-Ching Chen, Hsinchu (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Apr. 29, 2024, as Appl. No. 18/649,522.
Application 17/571,029 is a division of application No. 16/571,805, filed on Sep. 16, 2019, granted, now 11,222,843, issued on Jan. 11, 2022.
Application 18/649,522 is a continuation of application No. 17/571,029, filed on Jan. 7, 2022, granted, now 12,002,750.
Prior Publication US 2024/0290712 A1, Aug. 29, 2024
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5283 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An interconnect structure, comprising:
a first metal line and a second metal line in a first dielectric layer;
a catalyst layer on the first dielectric layer;
a dielectric block on the catalyst layer;
an etching stop layer along the second metal line, the catalyst layer and the dielectric block;
a second dielectric layer over the etching stop layer; and
a first via through the second dielectric layer and the etching stop layer on the first metal line, wherein a first interface between the etching stop layer and the second metal line is level to a second interface between the catalyst layer and the first dielectric layer.
 
9. An interconnect structure, comprising:
a first metal line, a second metal line and a third metal line surrounded by a first dielectric layer;
a first dielectric block over a first portion of the first dielectric layer between the first metal line and the second metal line;
a second dielectric block over a second portion of the first dielectric layer between the first metal line and the third metal line;
an etching stop layer along a side surface and a top surface of the first dielectric block and a side surface and a top surface of the second dielectric block; and
a first via landing on the first metal line and surrounded by the first dielectric block and the second dielectric block, wherein a first interface between the first via and the etching stop layer is aligned over a second interface between the first via and the first dielectric block.
 
15. An interconnect structure, comprising:
a first dielectric layer over a transistor;
a contact plug in the dielectric layer and electrically coupling to the transistor;
a second dielectric layer over the first dielectric layer, wherein the second dielectric layer includes a first dielectric material and a second dielectric material surrounded by the first dielectric material;
a first metal line in the second dielectric layer, wherein the first metal line includes a first metal material, a second metal material and a third metal material sequentially stacked;
a dielectric block over the second dielectric layer; and
a contact etching stop layer along a top surface of the third metal material of the first metal line and a sidewall and a top surface of the dielectric block, wherein the second metal material of the first metal line is separated from the contact etching stop layer by the third metal material of the first metal line.