| CPC H01L 23/5226 (2013.01) [H01L 21/76804 (2013.01); H01L 21/76879 (2013.01); H01L 23/5283 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 64/01 (2025.01)] | 14 Claims |

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1. An electronic package comprising:
a first layer;
a second layer; and
a via layer between the first layer and the second layer comprising an asymmetric via formed in the via layer, wherein the asymmetric via comprises:
a top side that contacts the second layer;
a bottom side that contacts the first layer, wherein the bottom side is parallel with the top side;
a first sidewall with a first slope angle in a first direction between the first layer and the second layer; and
a second sidewall with a second slope angle in the first direction between the first layer and the second layer, wherein the second slope angle is different from the first slope angle.
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