US 12,482,737 B2
Intelligent power module package structure and hybrid ceramic board
Chia-Shuai Chang, Hsin-Chu County (TW); Shu-Yi Liang, Taipei (TW); and Yan-Wei Chen, Taipei (TW)
Assigned to TONG HSING ELECTRONIC INDUSTRIES, LTD., Taipei (TW)
Filed by TONG HSING ELECTRONIC INDUSTRIES, LTD., Taipei (TW)
Filed on Aug. 7, 2023, as Appl. No. 18/366,662.
Claims priority of application No. 112115891 (TW), filed on Apr. 28, 2023.
Prior Publication US 2024/0363516 A1, Oct. 31, 2024
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 23/49811 (2013.01); H01L 23/49833 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 23/3121 (2013.01); H01L 23/49861 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49175 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An intelligent power module (IPM) package structure, comprising:
a ceramic carrier including:
an insulating ceramic layer having a first surface and a second surface that is opposite to the first surface;
a first conductive layer connected to the first surface, wherein the first conductive layer has a circuit layout slot that is recessed along a predetermined direction from an outer surface thereof to the first surface of the insulating ceramic layer, wherein the first conductive layer has a plurality of first circuits spaced apart from each other, and wherein any two of the first circuits adjacent to each other have a first conductor space therebetween that has a first minimal critical interval; and
a second conductive layer connected to the second surface;
a direct-plated copper (DPC) ceramic substrate disposed in the circuit layout slot and fixed onto the first surface, wherein a surrounding lateral side of the DPC ceramic substrate is not in contact with inner walls of the circuit layout slot so as to jointly form an annular gap therebetween, wherein along the predetermined direction, a top side of the DPC ceramic substrate and the outer surface of the first conductive layer have a step difference therebetween that is less than or equal to 300 μm, wherein the top side of the DPC ceramic substrate has a plurality of second circuits, and wherein any two of the second circuits adjacent to each other have a second conductor space therebetween that has a second minimal critical interval being less than the first minimal critical interval;
a plurality of first metal wires that are connected to the ceramic carrier and the DPC ceramic substrate so as to establish an electrical connection between the ceramic carrier and the DPC ceramic substrate;
a chip disposed on the first conductive layer of the ceramic carrier; and
a plurality of second metal wires that are connected to the chip and the DPC ceramic substrate so as to establish an electrical connection between the chip and the DPC ceramic substrate.