US 12,482,736 B2
Semiconductor device packages
Steven Verhaverbeke, San Francisco, CA (US); and Han-Wen Chen, Cupertino, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Oct. 26, 2022, as Appl. No. 17/973,690.
Claims priority of provisional application 63/278,424, filed on Nov. 11, 2021.
Prior Publication US 2023/0148220 A1, May 11, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01); H10B 80/00 (2023.01)
CPC H01L 23/49838 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/3675 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49894 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 23/562 (2013.01); H01L 24/08 (2013.01); H10B 80/00 (2023.02); H01L 24/16 (2013.01); H01L 2224/08235 (2013.01); H01L 2224/16235 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/3511 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A package assembly, comprising:
a core frame having a first surface opposite a second surface, the core frame further comprising:
a frame material that comprises silicon;
at least one cavity with a semiconductor die disposed therein, the semiconductor die having electrical contacts disposed on two opposing sides thereof; and
a via comprising a via surface that defines an opening extending through the core frame from the first surface to the second surface;
an insulating layer disposed over the first surface and the second surface, the insulating layer contacting at least a portion of each side of the semiconductor die; and
an electrical interconnection disposed within the via, wherein the insulating layer is disposed between the via surface and the electrical interconnection;
a stiffener frame formed over the insulating layer; and
a cladding layer disposed on the stiffener frame.