US 12,482,721 B2
Semiconductor package including heat dissipation structure
Yeonho Jang, Suwon-si (KR); Inhyung Song, Suwon-si (KR); Kyungdon Mun, Suwon-si (KR); and Hyeonjeong Hwang, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 16, 2023, as Appl. No. 18/197,998.
Claims priority of application No. 10-2022-0128083 (KR), filed on Oct. 6, 2022.
Prior Publication US 2024/0136250 A1, Apr. 25, 2024
Int. Cl. H01L 23/373 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 25/16 (2023.01)
CPC H01L 23/3738 (2013.01) [H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/0652 (2013.01); H01L 25/165 (2013.01); H01L 25/0657 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a package substrate;
a stacked chip disposed on the package substrate and comprising a lower chip and an upper chip;
a memory chip disposed on the package substrate adjacent to the stacked chip; and
an encapsulant encapsulating at least a portion of the stacked chip and the memory chip on the package substrate,
wherein an upper surface of the upper chip is exposed from the encapsulant, and
wherein a dummy silicon chip is in contact with the upper chip on the lower chip.