US 12,482,717 B2
Techniques for heat dispersion in 3D integrated circuit
Chien Ta Huang, Taoyuan (TW); Chun-Yang Tsai, Hsinchu (TW); Yi Ching Ong, Hsinchu (TW); Kuo-Ching Huang, Hsinchu (TW); and Harry-Hak-Lay Chuang, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 23, 2022, as Appl. No. 17/750,819.
Prior Publication US 2023/0378016 A1, Nov. 23, 2023
Int. Cl. H01L 23/367 (2006.01); H01L 21/768 (2006.01); H01L 23/373 (2006.01); H01L 23/528 (2006.01); H01L 25/04 (2023.01); H01L 25/11 (2006.01)
CPC H01L 23/367 (2013.01) [H01L 21/76801 (2013.01); H01L 23/3736 (2013.01); H01L 23/528 (2013.01); H01L 25/043 (2013.01); H01L 25/117 (2013.01); H01L 2224/24135 (2013.01); H01L 2924/18161 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a redistribution layer (RDL) stack of a 3D integrated circuit stack, comprising:
removing a substrate from a first side of a first die to expose a first dielectric layer;
forming a spiral trench in the first dielectric layer with one end of the spiral trench directly over a through silicon via (TSV) beneath the first dielectric layer;
forming a first barrier layer along sidewalls of the spiral trench, the first barrier layer being thermally coupled to the TSV; and
forming a first conductive wire within the spiral trench that is separated from the first dielectric layer by the first barrier layer, wherein the RDL stack is thermally coupled to the first die both through the TSV and through a composite dielectric between a semiconductor substrate of the first die and the first dielectric layer, while the semiconductor substrate and the first dielectric layer are electrically isolated from one another by the composite dielectric.