US 12,482,712 B2
Integrated circuit package and method of forming same
Chunho Kim, Phoenix, AZ (US); and Mark E. Henschel, Phoenix, AZ (US)
Assigned to Medtronic, Inc., Minneapolis, MN (US)
Filed by MEDTRONIC, INC., Minneapolis, MN (US)
Filed on Jan. 10, 2024, as Appl. No. 18/408,812.
Application 17/592,161 is a division of application No. 16/536,716, filed on Aug. 9, 2019, granted, now 11,270,920, issued on Mar. 8, 2022.
Application 18/408,812 is a continuation of application No. 17/592,161, filed on Feb. 3, 2022, granted, now 11,876,026.
Claims priority of provisional application 62/718,640, filed on Aug. 14, 2018.
Prior Publication US 2024/0145322 A1, May 2, 2024
Int. Cl. H01L 23/08 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/15 (2006.01); H01L 23/485 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/08 (2013.01) [H01L 21/486 (2013.01); H01L 21/56 (2013.01); H01L 23/15 (2013.01); H01L 23/485 (2013.01); H01L 23/5383 (2013.01); H01L 24/14 (2013.01); H01L 2924/1205 (2013.01); H01L 2924/1207 (2013.01); H01L 2924/13026 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An integrated circuit package, comprising:
an inorganic substrate comprising a glass core layer, wherein the glass core layer comprises a first major surface, a second major surface, and a cavity extending from the first major surface to the second major surface of the glass core layer;
a die disposed in the cavity of the glass core layer;
an encapsulant disposed in the cavity between the die and a sidewall of the cavity;
a first patterned conductive layer disposed adjacent the first major surface of the glass core layer;
a second patterned conductive layer disposed adjacent the second major surface of the glass core layer;
a conductive via disposed in the glass core layer and extending between the first and second major surfaces of the glass core layer, wherein the conductive via is electrically connected to at least one of the first and second patterned conductive layers; and
a device disposed on the first patterned conductive layer, wherein the device is electrically connected to the die;
wherein the die is electrically connected to at least one of the first and second patterned conductive layers.