US 12,482,710 B2
Method of fabricating array substrate with testing pins
Yu Ai, Beijing (CN); Xuewu Xie, Beijing (CN); Bowen Liu, Beijing (CN); Yubao Kong, Beijing (CN); Shi Sun, Beijing (CN); Hao Liu, Beijing (CN); and Ameng Zhang, Beijing (CN)
Assigned to Hefei Xiasheng Optoelectronics Technology Co., Ltd., Anhui (CN); and Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 17/417,050
Filed by Hefei Xinsheng Optoelectronics Technology Co., Ltd., Anhui (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Sep. 9, 2020, PCT No. PCT/CN2020/114189
§ 371(c)(1), (2) Date Jun. 21, 2021,
PCT Pub. No. WO2022/051929, PCT Pub. Date Mar. 17, 2022.
Prior Publication US 2022/0319937 A1, Oct. 6, 2022
Int. Cl. H01L 21/66 (2006.01); H01L 21/67 (2006.01); H01L 27/12 (2006.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC H01L 22/34 (2013.01) [H01L 21/67288 (2013.01); H01L 22/14 (2013.01); H10D 86/021 (2025.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A method of fabricating an array substrate, comprising:
providing a substrate comprising a gate pad configured to be bonded to a gate driving integrated circuit, a data pad configured to be bonded to a data driving integrated circuit, and a plurality of first connecting lines connecting the gate pad and the data pad;
forming a testing pad on the substrate;
forming a shorting bar connecting the testing pad to first terminals of the plurality of first connecting lines;
forming a plurality of testing pins respectively connected to second terminals of the plurality of first connecting lines, wherein the plurality of testing pins are formed in a first dummy region of the substrate, the first dummy region is adjacent to an array substrate region of the substrate; and
connecting the plurality of testing pins to a probe unit to test connectivity of the plurality of first connecting lines.