US 12,482,649 B2
Semiconductor device with porous layer and method for fabricating the same
Tse-Yao Huang, Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on May 19, 2023, as Appl. No. 18/199,455.
Prior Publication US 2024/0387165 A1, Nov. 21, 2024
Int. Cl. H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/02203 (2013.01) [H01L 21/0334 (2013.01); H01L 21/76835 (2013.01); H01L 21/76846 (2013.01); H01L 21/76876 (2013.01); H01L 23/5283 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 23/53295 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a bottom interconnector layer positioned in the substrate;
a bottom dielectric layer positioned on the substrate;
an interconnector structure positioned along the bottom dielectric layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer;
a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure; and
a top dielectric layer positioned surrounding the top glue layer;
wherein a top surface of the interconnector structure, a top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar;
wherein the top dielectric layer is porous.