US 12,482,521 B2
Non-volatile phase-change memory device including a distributed row decoder with n-channel MOSFET transistors and related row decoding method
Antonino Conte, Tremestieri Etneo (IT); Alin Razafindraibe, Saint Martin d'Hères (FR); Francesco Tomaiuolo, Acireale (IT); and Thibault Mortier, Grenoble (FR)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT); and STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR); and STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Jan. 6, 2024, as Appl. No. 18/406,097.
Application 18/406,097 is a continuation of application No. 17/667,080, filed on Feb. 8, 2022, granted, now 11,908,514.
Claims priority of application No. 102021000004973 (IT), filed on Mar. 3, 2021.
Prior Publication US 2024/0153553 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0028 (2013.01) [G11C 13/0004 (2013.01); G11C 13/003 (2013.01); G11C 2213/79 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory device, comprising:
a plurality of local pull-up stages distributed along a group of memory portions in a memory array, each local pull-up stage comprising, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type, wherein the local pull-up transistors of each local pull-up stage are configured to:
locally decouple the corresponding wordline from a node at a first reference potential in response to a wordline that extends through the group of memory portions being selected, and
locally couple the corresponding wordline to the node at the first reference potential in response to all the wordlines that extend through the group of memory portions being deselected to restore locally a deselection voltage on a wordline previously selected.